The present invention relates to power-on-reset circuits.
In integrated circuits, and particularly in micro-logic circuits, there is often the necessity of integrating therewith specific circuits capable of ensuring the resetting of all the functional elements of the integrated circuit to a certain state whenever power is switched on. This resetting must occur independently of the manner in which the supply voltage is raised from ground potential to the nominal supply voltage level, in order to prevent the occurrence of undesired and unforeseen configurations of the integrated circuit, which may cause malfunctioning and possibly latching of the whole integrated circuit device.
Such circuits are called power-on reset circuits, and are commonly referred to by the acronym "POR". POR circuits perform the aforementioned function. These circuits are capable of generating a resetting pulse of predetermined characteristics upon the switching on of the integrated circuit.
Generally, these POR circuits have an architecture which includes power dissipative, static current paths between the supply voltage nodes and, although these static current paths normally have a relatively high impedance, the persistence of a non-negligible static power consumption is not, in many cases, compatible with design specifications of CMOS integrated circuit devices, which typically have a null-static consumption. This problem is felt even more in special CMOS circuit devices which are destined to function for very short periods of time while being powered solely by the electrical charge stored in an electrolytic capacitor (e.g. of several .mu.F), wherein the static consumption caused by the power-on reset circuit assumes great relevance.
These power-on reset circuits may themselves be a cause of malfunctioning if they are likely to be accidentally triggered by internal or external transients, i.e. noise.
Power-on reset circuits commonly have a structure such as the one which is shown in FIG. 1, which comprises two inverters (the first of which is formed by the complementary pair of transistors M5 and M4 and the second is indicated by the block I) connected in cascade. The output of the second inverter I coincides with the output node of the circuit. A voltage monitoring branch (voltage driver) is connected between the supply node and ground to detect the voltage which is actually present on the supply node, and may comprise (for example) at least two directly biased junctions connected in series to each other (realized, in the example shown, with two diode-configured transistors M1 and M2, and a resistance R1). The intermediate node Vx of this voltage sensing branch drives the first inverter through the gate electrode of the M4 transistor. The capacitance C1 represents the capacitive coupling of the node Vx toward ground potential. The M3 transistor is driven by the voltage which is present on the intermediate connection node A between the two inverters and determines the dropping to zero of the reset signal produced by the POR circuit when the voltage Vx reaches the triggering threshold of the first inverter, that is when the voltage on the supply node has reached a safety level which is sufficiently high in its rise toward the nominal value VDD. In fact, at that point, the voltage on the A node becomes low, thus switching-off the M3 transistor, while the M1 and M2 junctions are kept conducting by R1.
The drawback of such a circuit is current consumption. In fact, when the supply voltage has reached the nominal working level, R1 continues to draw a non-negligible current which, for a value of R1 of 300K.OMEGA. and a supply voltage (VDD) of 5V, may be about 6.6 .mu.A. In many instances, such a current static absorption may be outside the specifications of the particular integrated circuit.
The present invention provides a power-on reset (POR) circuit which has the advantages of reduced static power consumption and enhanced immunity to noise.
Basically, the method herein proposed for reducing the current absorption under static condition of a power-on reset circuit comprises biasing with an extremely low current a pair of transistors functionally utilized in the supply voltage monitoring branch, until the supply voltage remains relatively low. This has the purpose and effect of bringing said transistors into a condition normally referred to as "subthreshold" operation. This is a peculiar condition of operation proper of field effect (MOS) transistors which occurs for gate-to-source voltages close to the transistor's threshold voltage. Under these bias conditions, the MOS transistor conducts an extremely low current and the input-to-output transfer characteristic becomes exponential instead of being quadratic. Such an operation condition is amply described in the article entitled "CMOS Analog Integrated Circuits Based on Weak Inversion Operation" by Eric Vittoz and Jean Fellrath, 12 IEEE JOURNAL OF SOLID-STATE CIRCUITS 224 (June 1977), which is hereby incorporated by reference.
Thus, the presently preferred embodiment provides a power-on-reset circuit which employs a supply voltage sensing branch for triggering a first inverter of a pair of cascaded inverters. The intrinsic static consumption of such a POR circuit is strongly reduced by employing a current generator, which is automatically forced to deliver a reduced current during the operation of the integrated circuit, for biasing two transistors functionally connected in said voltage sensing branch into a subthreshold operating condition.
The disclosed inventions teach use of a reference current generator having a characteristic defined by the ratio .delta.Vbe/R, by the use of which a first bias current is delivered to a pull-up element of the first inverter of the circuit according to a certain current-mirror ratio, and a second bias current is delivered to a first element of said supply voltage monitoring branch which is functionally connected to the supply node, in order to force a certain current through this sensing branch. The intermediate node of connection in cascade between two inverters of the circuit drives a second element capable of being biased and functionally connected to ground of the supply voltage sensing branch, as well as a control terminal of the current generator, through which the current delivered by the generator may be modified in order to reduce it during the periods of operation of the integrated circuit.